Annoted layout of the circuit
Statistics of the design obtained through simulation
Un-annoted layout
Gate drawing of the logic
Project information
- Category: Digital Design, Layout
- Completion date: June 2022
- Technologies: Cadence, Digital Design
Details
For the Digital Electronic Circuits course (ECE 115C) and accompanying honors seminar (ECE 189) at UCLA, I built a 4-bit absolute absolute value threshold detector in Cadence. In a group of 3, I designed, simulated, and laid out an integrated circuit that detects when a 4-bit 2's complement number exceeds a threshold value.